Clock divider on More Triggers 16 (9-16)

[mgd]

I don't get it..

What is the TRBH/TRBL fx doing?
I don't get any "clock divided" Trigger out of the Trigger 16 Outputs..

Can someone please explain?

TRBH and TRBL are setting all 8 outputs of the higher/lower byte at once. I'll try to explain using TRBL for outputs 1-8. TRBH is doing the same only for outputs 9-16.

Assume you want 1 to be high, 2,3 and 4 low, 5 and 6 high, 7 low and 8 high.
Binary that would be 1 0 0 0 1 1 0 1 (outputs 1-8). However the TRBL/TRBH commands have the LSB (==Least Significant Bit) as outs 1 and 9 respectively. So you have to reverse the order:
Binary that would be 1 0 1 1 0 0 0 1 (outputs 8-1). In Hexadecimal that is B1.

Now let's add FX+* to this. We start by TRBL 01 (output 1 -> on, outputs 2-8 -> off).
Next step use FX+* with 01. That changes TRBL 01 into TRBL 02 (effectively switching output 1 -> off, output 2 -> on and leave the rest unchanged).
Next step use FX+* with 01 again. That changes TRBL 02 into TRBL 03 (effectively switching output 1 -> on, leaving output 2 -> on and leave the rest unchanged).
Next step use FX+* with 01 again. That changes TRBL 03 into TRBL 04 (effectively switching output 1 -> off, switching output 2 -> off, switching output 3 -> on and leave the rest unchanged).
And so on.
For the 64 steps of a pattern the state of the outputs 8-1 will be:

Code:

00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
...
00011111
00100000
00100001
00100010
...
00111111
01000000

Note that these are NOT triggers bit gates and that's essentially what a clock divider does.

Hope that clarifies things a bit. If not feel free to ask and I'll try to elaborate a bit firther.

Kind regards,
Michael

Update: You could as well start with TRBL 00, then the first bit pattern will be 00000000 and the last will be be 00111111 and all the rest remains the same.